A methodology for mapping from user-visible core, CHA, and memory controller numbers to locations on the processor die is presented, along with results obtained from systems with Intel Xeon Phi x200 (“Knights Landing”, “KNL”) processors at the Texas Advanced Computing Center. The current methodology is based on the data traffic counters in the 2-D mesh on-chip-network, with the measurements revealing unexpected and counterintuitive transformations of the meanings of “left”, “right”. “up”, and “down” in different regions of the chip. For the systems tested, all CHAs were active and had the same mapping of CHA number to physical location on the die. In contrast to our observations with Xeon Scalable Processors, the x2APIC IDs of the cores in Xeon Phi x200 are not mapped independently of the CHAs – the x2APIC ID of any enabled core contains the CHA number in bits [8:3]. Disabled cores are identified by x2APIC values not seen in any active core. In all cases tested, Logical Processor numbers were assigned to the active physical cores using a simple monotonic mapping.